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| DUAL SONET OC-12 CLOCK SYNTHESIZER FEATURES s Two independently-powered 622.08MHz clock sources one chip s Differential PECL outputs s TTL/CMOS compatible inputs s SONET compliant jitter performance (0.01UI) s Choice of three reference frequencies for each PLL s Only 395mW per PLL (typ) s Complies with Bellcore, CCITT and ANSI standards s Single +5 volt power supply s Fully compatible with industry standard 10KH I/O levels s Available in 28-pin PLCC package ClockWorksTM SY89425 DESCRIPTION Micrel-Synergy's SY89425 Dual Phase Locked Loop (PLL) consists of two totally separate, SONET compliant 622.08MHz clock generators on one chip. The user may select to power both PLLs or PLL A only. Each PLL produces a low-jitter OC-12/STS-12 clock rate from an input reference clock of 38.88, 51.84, or 77.76MHz. When using both PLLs, it is not necessary that they share a common reference clock (e.g., PLL A may operate from an STS-1 reference of 51.84MHz, while PLL B operates from an OC-3/STS-3 reference of 77.76MHz). The SY89425 operates from a single +5 volt supply, and requires only a simple series RC loop filter for each PLL. Coupling Micrel-Synergy's advanced PLL technology with our proprietary ASSETTM bipolar process has produced a clock generator IC which exceeds applicable Bellcore and ANSI specifications, while setting a new standard for performance and flexibility. TYPICAL APPLICATION +5V +5V PIN CONFIGURATION FLTRAN FLTRAP RSTA VCCA GND GND RFCKA (TTL) VCCA VCCOA RSTA (TTL) 25 24 23 22 21 20 19 VCCA GND CLOCK IN 0.1uF SEL39A SEL78A RFCKA VCCA 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 16 CK622AP CK622AN VCCOA GND VCCOB CK622BN CK622BP FLTRAN FLTRAP PLL A CK622AP (PECL) CK622AN PLCC TOP VIEW 15 14 13 12 RFCKB 622.08MHz SEL78B SEL39B 500 SEL39A (TTL) SEL78A (TTL) 2X 50 GND GND FLTRBN FLTRBP RSTB VCCB +3V PLL B GND AGND (SAME AS PLL A) VCCB Rev.: E Amendment: /0 1 Issue Date: August, 1998 Micrel ClockWorksTM SY89425 FUNCTIONAL BLOCK DIAGRAM VCCA 2 GND 3 FLTRAP/N VCCOA RSTA (TTL) RFCKA (TTL) /f CHG PUMP 622MHz VCO FEEDBACK DIVIDER (8/12/16) SEL39A (TTL) SEL78A (TTL) CK622AP (PECL) CK622AN PLL A PLL B FEEDBACK DIVIDER (8/12/16) CK622BP (PECL) CK622BN SEL78B (TTL) SEL39B (TTL) RFCKB (TTL) /f CHG PUMP 622MHz VCO RSTB (TTL) 3 2 GND FLTRBP/N VCCB VCCOB 2 Micrel ClockWorksTM SY89425 PIN DESCRIPTION INPUTS RFCKB [Reference Clock B] TTL Reference clock in for PLL B. (38.88, 51.84 or 77.76MHz). SEL39B [38.88MHz Select B] TTL Logic HIGH on this pin denotes a 38.88MHz input reference clock for PLL B. Tie to logic LOW if input is not 38.88MHz. SEL78B [77.76MHz Select B] TTL Logic HIGH on this pin denotes a 77.76MHz input reference clock for PLL A. Tie to logic LOW if input is not 77.76MHz. RSTB [Reset B] TTL Tie to logic LOW for normal operation; logic HIGH forces reset of internal Phase Detector & feedback dividers on PLL B. FLTRBP, FLTRBN (Loop Filter B, Pos & Neg) Analog. Connect a series RC loop filter between these pins. The suggested loop filter is 0.1F and 500 ohms, as shown in the typical application on page 3-9. RSTA (Reset A) TTL Tie to logic LOW for normal operation; logic HIGH forces reset of internal Phase Detector & feedback dividers on PLL A. SEL78A [77.76MHz Select A] TTL Logic HIGH on this pin denotes a 77.76MHz input reference clock for PLL A. Tie to logic LOW if input is not 77.76MHz. SEL39A [38.88MHz Select A] TTL Logic HIGH on this pin denotes a 38.88MHz input reference clock for PLL A. Tie to logic LOW if input is not 38.88MHz. REFCKA [Reference Clock A] TTL Reference clock in for PLL A. FLTRAP, FLTRAN (Loop Filter A, Pos & Neg) Analog. Connect a series RC loop filter between these pins. The suggested loop filter is 0.1F and 500 ohms, as shown in the typical application on page 5-527. OUTPUTS CK622BP, CK622BN (Clock Out B) Differential PECL 622.08MHz output clock from PLL B. CK622AP, CK622AN (Clock Out A) 622.08MHz output clock from PLL A. POWER & GROUND VCCA VCCB VCCOA VCCOB GND +5V for PLL A. +5V for PLL B. +5V for PLL A PECL outputs. +5V for PLL B PECL outputs. Ground (0 volts) Differential PECL REFERENCE FREQUENCY SELECTION SEL39 0 0 1 1 SEL78 0 1 0 1 fRFCK 51.84 77.76 38.88 77.76 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VI IOUT TA Tstore Power Supply Input Voltage Output Current Operatimg Temperature Range Storage Temperature Range -Continuous -Surge Parameter Rating 0 to +7 0 to VCC 50 100 0 to +85 -65 to +150 Unit V V mA C C NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. 3 Micrel ClockWorksTM SY89425 PECL DC ELECTRICAL CHARACTERISTIC(1), (2) VCCA = VCCB = VCCOA =VCCOB = +5V 5%; GND = 0V; TA = 0C to 85C TA = -40C Symbol VOH VOL VIH VIL IIL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current (1) TA = 0C Min. Max. TA = +25C Min. Max. TA = +85C Min. VCC -960 Max. VCC -670 Unit mV mV mV mV A Min. Max. VCC -1130 VCC -840 VCC -1070 VCC -2000 VCC -1600 VCC -2000 VCC -1230 VCC -890 VCC -1170 VCC -1950 VCC -1500 VCC -1950 0.5 -- 0.5 VCC -790 VCC -1030 VCC -760 VCC -1580 VCC -2000 VCC -1580 VCC -2000 VCC -1545 VCC -840 VCC -1130 VCC -810 VCC -1060 VCC -720 VCC -1480 VCC -1950 VCC -1480 VCC -1950 VCC -1445 -- 0.5 -- 0.3 -- (1) NOTES: 1. Forcing one input at a time. Apply VIH (Max) or VIL (Min) to all other inputs. 2. Airflow greater than 500lfpm is maintained. TTL DC ELECTRICAL CHARACTERISTICS VCCA = VCCB = VCCOA =VCCOB = +5V 5%; GND = 0V; TA = 0C to 85C Symbol VOH VOL IOS VIH VIL Parameter Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Input HIGH Voltage Input LOW Voltage Min. 2.4 -- -150 2.0 -- Max. -- 0.5 -60 -- 0.8 Unit V V mA -- V Condition IOH = -2mA IOL = 4mA VOUT = 0V -- -- DC ELECTRICAL CHARACTERISTICS(1), (2), (3) TTL DC ELECTRICAL CHARACTERISTICS -- VCCA = VCCB = VCCOA =VCCOB = +5V 5%; GND = 0V; TA = 0C to 85C Symbol IEE IOUT Parameter Internal Operating Current Termination Output Current Min. -- -- Typ. 157 11 Max. 204 -- Unit mA mA Condition Both PLLs powered 50 to Vcc -2, 50% duty cycle NOTES: 1. To calculate total power supply current into the VCC pins: ICC = (n * IOUT); where n = number of ECL output pins used (ie, terminated). 2. To calculate total device power dissipation; PD = [IEE * (VCC - VEE)] + [n * IOUT * 1.33](3). 3. Average ECL output voltage is calculated as VOAVG = (VOH(MAX) + VOH(MIN) + VOL(MAX) + VOL(MIN)) /4 = 1.33V. 4 Micrel ClockWorksTM SY89425 AC ELECTRICAL CHARACTERISTICS VCCA = VCCB = VCCOA =VCCOB = +5V 5%; GND = 0V; TA = 0C to 85C Parameter VCO Center Frequency Reference Clock (RFCK) Frequency Tolerance Reference Clock (RFCK) Input Duty Cycle Acquisition Lock Time TTL Output Rise/Fall Time PECL Output Rise/Fall Time CK622 Output Duty Cycle tRST - RST pulse width tp622 Static Phase Offset of CK622 -- -- -- 45 -- -- -- 45 1 -- Min. Typ. 622.08 1% 20 20 10 -- -- -- -- -- -- -0.7 -- -- -- 55 15 2 500 55 -- -- Max. Units MHz ppm ppm ppm % of UI sec ns ps % of UI sec ns 10% to 90% of amplitude, 15pF load 10% to 90%, 50 load, 5pF cap Condition Nominal 77.76MHz 51.84MHz 38.88MHz DC ELECTRICAL CHARACTERISTICS -- TTL TIMING WAVEFORMS RFCK Input tp 622 CK622 Output 5 Micrel ClockWorksTM SY89425 JITTER GENERATION Jitter Generation Definition Bellcore TR-NWT-000499 (Issue 4), section 7.3.3 "Jitter generation is the process whereby jitter appears at the output port of an individual unit of digital equipment in the absence of applied input jitter." Jitter Generation Requirement Bellcore TA-NWT-000253 (Issue 2), section 5.6.5.2 "For Category II interfaces, jitter generation shall not exceed 0.01 UI rms. For OC-N and STSX-N interfaces, a high-pass measurement filter with a 12kHz cutoff frequency shall be used." The low-pass cutoff frequency of the measurement filter shall be higher than 5MHz. The characteristic of the measurement filter is shown below. SONET OC-12 Category II Jitter Generation Measurement Filter Characteristics UI (rms) 0.01 +20dB/decade 12kHz Frequency 5MHz (minimum) Figure 1 PRODUCT ORDERING CODE Ordering Code SY89425JC SY89425JCTR Package Type J28-1 J28-1 Operating Range Commercial Commercial 6 Micrel ClockWorksTM SY89425 28 LEAD PLCC (J28-1) Rev. 03 7 Micrel ClockWorksTM SY89425 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 8 |
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